Altera CPRI v6.0 MegaCore Function - Manual (Page 51)

Direct IQ Interface
If you turn on Enable direct IQ mapping interface in the CPRI v6.0 parameter editor, the direct IQ
interface is available. This interface allows direct access to the I/Q data time slots in the CPRI frame. You
can connect this interface to any user-defined air standard I/Q mapping module.
This interface is Avalon-ST compliant with a read latency value of 1.
You can alter the transmit latency with the Auxiliary latency cycle(s) parameter.
Table 3-6: Direct IQ Interface Signals
All interface signals are clocked by the
cpri_clkout
clock.
Direct IQ RX Interface
Signal Name Direction Description
iq_rx_valid[3:0]
Output Each asserted bit indicates the corresponding byte on the
current
iq_rx_data
bus is valid I/Q data.
iq_rx_data[31:0]
Output I/Q data received from the CPRI frame. The
iq_rx_valid
signal indicates which bytes are valid I/Q data bytes.
Direct IQ TX Interface
Signal Name Direction Description
iq_tx_ready[3:0]
Output Each asserted bit indicates the IP core is ready to read I/Q
data from the corresponding byte of
iq_tx_data
on the
next clock cycle.
iq_tx_valid[3:0]
Input Write valid for
iq_tx_data
. Assert bit [n] to indicate that
the corresponding byte on the current
iq_tx_data
bus is
valid I/Q data.
iq_tx_data[31:0]
Input I/Q data to be written to the CPRI frame. The IP core
writes the individual bytes of the current value on the
iq_
tx_data
bus to the CPRI frame based on the
iq_tx_ready
signal from the previous cycle, and the
iq_tx_valid
signal in the current cycle.
UG-01156
2014.08.18
Direct IQ Interface 3-21
Functional Description Altera Corporation
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