Altera CPRI v6.0 MegaCore Function User Manual
Page 56
Table 3-8: Real-Time Vendor Specific Interface Signals
All interface signals are clocked by the
cpri_clkout
clock.
Real-Time Vendor Specific RX Interface
Signal Name
Direction
Description
rtvs_rx_valid
Output
Each asserted bit indicates the corresponding byte on the
current
rtvs_rx_data
bus is a valid real-time vendor-
specific byte.
rtvs_rx_data[31:0]
Output
Real-time vendor-specific word received from the CPRI
frame. The
rtvs_rx_valid
signal indicates which bytes
are valid real-time vendor-specific bytes.
Real-Time Vendor Specific TX Interface
Signal Name
Direction
Description
rtvs_tx_ready
Output
Indicates the IP core is ready to read a real-time vendor-
specific byte from
rtvs_tx_data
on the next clock cycle.
rtvs_tx_valid
Input
Write valid for
rtvs_tx_data
. Assert this signal to
indicate
rtvs_tx_data
holds a valid value in the current
clock cycle.
rtvs_tx_data[31:0]
Input
Real-time vendor-specific word to be written to the CPRI
frame. The IP core writes the current value of the
rtvs_
tx_data
bus to the CPRI frame based on the
rtvs_tx_
ready
signal from the previous cycle, and the
rtvs_tx_
valid
signal in the current cycle.
Figure 3-18: Direct RTVS RX Timing Diagram
Direct RTVS RX interface behavior in a CPRI v6.0 IP core running at 10.1376 Gbps.
The
aux_rx_x
and
aux_rx_seq
signals are not part of this interface and are available only if you turn on
the AUX interface in your CPRI v6.0 IP core variation. However, their presence in the timing diagram
explains the timing of the
rtvs_rx_valid
output signal that you use to identify the clock cycles with valid
RTVS data.
cpri_clkout
100
101
124
7
4
6
aux_rx_x
aux_rx_seq
rtvs_rx_valid
X
D1D2D3D4
X
rtvs_rx_data[31:0]
5
4
3
2
1
0
79
3
2
1
0
D5D6
X
3-26
Real-Time Vendor Specific Interface
UG-01156
2014.08.18
Altera Corporation
Functional Description