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Media Independent Interface (MII) to External Ethernet Block........................................................ 3-32
CPU Interface to CPRI v6.0 IP Core Registers...................................................................................... 3-35
CPU Interface Signals....................................................................................................................3-36
Accessing the Hyperframe Control Words................................................................................3-37
Auto-Rate Negotiation..............................................................................................................................3-40
Extended Delay Measurement................................................................................................................. 3-41
Extended Delay Measurement Interface.....................................................................................3-43
Deterministic Latency............................................................................................................................... 3-43
CPRI v6.0 IP Core Transceiver and Transceiver Management Interfaces........................................ 3-45
CPRI Link........................................................................................................................................3-45
Main Transceiver Clock and Reset Signals.................................................................................3-46
Arria V GZ and Stratix V Transceiver Reconfiguration Interface..........................................3-46
Arria 10 Transceiver Reconfiguration Interface........................................................................3-46
Interface to the External Reset Controller..................................................................................3-47
Interface to the External PLL........................................................................................................3-48
Transceiver Debug Interface........................................................................................................ 3-49
Testing Features......................................................................................................................................... 3-49
CPRI v6.0 IP Core Loopback Modes...........................................................................................3-49
CPRI v6.0 IP Core Self-Synchronization Feature......................................................................3-50
CPRI v6.0 IP Core Signals...................................................................................4-1
CPRI v6.0 IP Core L2 Interface..................................................................................................................4-1
CPRI v6.0 IP Core L1 Direct Access Interfaces....................................................................................... 4-2
CPRI v6.0 IP Core Management Interfaces............................................................................................. 4-4
CPRI v6.0 IP Core Transceiver and Transceiver Management Signals............................................... 4-6
CPRI v6.0 IP Core Registers................................................................................5-1
INTR Register...............................................................................................................................................5-3
L1_STATUS Register...................................................................................................................................5-3
L1_CONFIG Register..................................................................................................................................5-4
BIT_RATE_CONFIG Register...................................................................................................................5-5
PROT_VER Register................................................................................................................................... 5-6
TX_SCR Register..........................................................................................................................................5-7
RX_SCR Register..........................................................................................................................................5-7
CM_CONFIG Register................................................................................................................................5-8
CM_STATUS Register................................................................................................................................ 5-9
START_UP_SEQ Register..........................................................................................................................5-9
START_UP_TIMER Register.................................................................................................................. 5-10
FLSAR Register...........................................................................................................................................5-11
CTRL_INDEX Register.............................................................................................................................5-11
TX_CTRL Register.....................................................................................................................................5-12
RX_CTRL Register.....................................................................................................................................5-13
RX_ERR Register....................................................................................................................................... 5-13
RX_BFN Register.......................................................................................................................................5-14
LOOPBACK Register................................................................................................................................ 5-14
TX_DELAY Register................................................................................................................................. 5-16
RX_DELAY Register................................................................................................................................. 5-17
CPRI v6.0 MegaCore Function User Guide
TOC-3
Altera Corporation
