Kontron S5500 SEL Troubleshooting - Manual (Page 65)

Memory subsystem System Event Log Troubleshooting Guide for Intel® S5500/S3420 series Server Boards
56 Intel order number G74211-001 Revision 1.0
9.1.4 Sparing Redundancy State Sensor
This sensor provides the RAS Redundancy state for the Spare Channel Mode.
Table 58: Sparing Redundancy State Sensor Typical Characteristics
Byte Field Description
8
9
Generator ID 0001h = BIOS POST
11 Sensor Type 0ch = Memory
12 Sensor Number 11h
13
Event Direction and
Event Type
[7] Event direction
0b = Assertion Event
1b = Deassertion Event
[6:0] Event Type = 0Bh (Generic Discrete)
14 Event Data 1
[7:6] – 10b = OEM code in Event Data 2
[5:4] – 10b = OEM code in Event Data 3
[3:0] – Event Trigger Offset as described in Table 59
15 Event Data 2
[7:4] – If Domain Instance Type (ED3) is set to Local, this field specifies the 0-based Socket ID of the processor that contains the sparing
domain local sub-instances.
A value of 1110b indicates that the sparing configuration specified in Bits [3:0] applies globally to all sockets in the system.
If Domain Instance Type (ED3) is set to Global, this field specifies the 0-based Socket ID of the second participant processor in this
sparing domain global instance.
A value of 1111b indicates that this field is unused and does not contain valid data.
[3:0] – If Domain Instance Type (ED3) is set to Local, this field specifies the sparing domain local sub-instances – which channels are
included in this sub-instance:
0000b – Reserved
0001b – {Ch A, Ch B, Ch C} (only configuration possible on Intel ® S5500/S5520 Server Boards)
0010b - 1110b – Reserved
If Domain Instance Type (ED3) is set to Global, this field specifies the 0-based Socket ID of the first participant processor in this
sparing domain global instance.
A value of 1111b indicates that this field is unused and does not contain valid data.