NEC PD754144 - Manual (Page 97)

CHAPTER 6 PERIPHERAL HARDWARE FUNCTION
97 User’s Manual U10676EJ3V0UM
Table 6-2. I/O Pin Manipulation Instructions
PORT PORT3 PORT6 PORT7 PORT8
Instruction
IN A, PORTn Note 1
IN XA, PORTn Note 1 –
OUT PORTn, A Note 1 –
OUT PORTn, XA Note 1 –
MOV A, PORTn Note 1
MOV XA, PORTn Note 1 –
MOV PORTn, A Note 1
MOV PORTn, XA Note 1 –
XCH A, PORTn Note 1
XCH XA, PORTn Note 1 –
MOV1 CY, PORTn. bit
MOV1 CY, PORTn. @L Note 2
MOV1 PORTn. bit, CY –
MOV1 PORTn. @L, CY Note 2 –
INCS PORTn Note 1
SET1 PORTn. bit
SET1 PORTn. @L Note 2
CLR1 PORTn. bit
CLR1 PORTn. @L Note 2
SKT PORTn. bit
SKT PORTn. @L Note 2
SKF PORTn. bit
SKTCLR PORTn. bit
SKTCLR PORTn. @L Note 2
SKF PORTn. @L Note 2
AND1 CY, PORTn. bit
AND1 CY, PORTn. @L Note 2
OR1 CY, PORTn. bit
OR1 CY, PORTn. @L Note 2
XOR1 CY, PORTn. bit
XOR1 CY, PORTn. @L Note 2
Notes 1. Must be MBE = 0 or (MBE = 1, MBS = 15) before execution.
2. The lower 2 bits and the bit addresses of the address must be indirectly specified by the L register.