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NEC PD754144 User Manual

Page 225

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CHAPTER 8 STANDBY FUNCTION

225

User’s Manual U10676EJ3V0UM

(2) Application example of HALT mode (when using the

µPD754244 at f

X

= 6.0 MHz)

• The standby mode is set at the falling edge of INT0 and released at the rising edge.

• In the standby mode, an intermittent operation is performed at intervals of 175 ms (INTBT).

• INT0 and INTBT are assigned a lower priority.

• The slowest CPU clock is selected in the standby mode.

P61/INT0

0 V

V

DD

V

DD

pin voltage

INT0

INT0

Operation

mode

CPU operation

Intermittent operation

(HALT mode + Iow-speed operation)

Operation mode

(low-speed)

175 ms

Operation mode

(high-speed)

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