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NEC PD754144 User Manual

Page 139

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CHAPTER 6 PERIPHERAL HARDWARE FUNCTION

139

User’s Manual U10676EJ3V0UM

[Timer set time] (cycle) is calculated by dividing [contents of modulo register + 1] by [count pulse (CP)

frequency] selected by the mode register.

T (sec) =

= (n+1) (resolution)

where,

T (sec): Timer set time (seconds)

f

CP

(Hz): CP frequency (Hz)

n:

Contents of modulo register (n

≠ 0)

Once the timer has been set, interrupt request flag IRQTn is set at the set time interval of the timer.

Table 6-7 shows the resolution of each count pulse of the timer counter and the longest set time (time when FFH

is set to the modulo register).

Table 6-7. Resolution and Longest Set Time (8-Bit Timer Counter Mode) (1/3)

(TM10 = 0, TM11 = 0, TM20 = 0, TM21 = 0)

(a)

µPD754244: at 6.0 MHz

8-bit timer counter (channel 0)

Mode Register

8-bit Timer Counter (Channel 0)

TM06

TM05

TM04

Resolution

Longest set time

1

0

0

171

µs

43.7 ms

1

0

1

42.7

µs

10.9 ms

1

1

0

10.7

µs

2.73 ms

1

1

1

2.67

µs

683

µs

8-bit timer counter (channel 1)

Mode Register

8-bit Timer Counter (Channel 1)

TM16

TM15

TM14

Resolution

Longest set time

0

1

1

5.33

µs

1.37 ms

1

0

0

683

µs

175 ms

1

0

1

171

µs

43.7 ms

1

1

0

42.7

µs

10.9 ms

1

1

1

10.7

µs

2.73 ms

n +1

f

CP

.

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