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9 bank select register (bs) – NEC PD754144 User Manual

Page 78

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CHAPTER 4 INTERNAL CPU FUNCTION

78

User’s Manual U10676EJ3V0UM

4.9 Bank Select Register (BS)

The bank select register (BS) consists of a register bank select register (RBS) and a memory bank select register

(MBS) which specify the register bank and the memory bank to be used, respectively.

RBS and MBS are set by the SEL RBn and SEL MBn instructions, respectively.

BS can be saved to or restored from the stack area in 8-bit units by the PUSH BS or POP BS instruction.

Figure 4-14. Configuration of Bank Select Register

RBS0

RBS1

0

0

MBS0

MBS1

MBS2

MBS3

F82H

F83H

Symbol

BS

Address

F82H

(1) Memory bank select register (MBS)

The memory bank select register is a 4-bit register that records the higher 4 bits of a 12-bit data memory

address. This register specifies the memory bank to be accessed. With the

µPD754244, however, only banks

0, 4 and 15 can be specified.

MBS is set by the SEL MBn instruction (n = 0, 4, 15).

The address range specified by MBE and MBS is as shown in Figure 3-2.

When the RESET signal is asserted, MBS is initialized to “0”.

Table 4-6. MBE, MBS, and Memory Bank Selected

MBE

MBS

Memory Bank

3

2

1

0

0

Ч

Ч

Ч

Ч

Fixed to memory bank 0

1

0

0

0

0

Selects memory bank 0

0

1

0

0

Selects memory bank 4

1

1

1

1

Selects memory bank 15

Other than above

Setting prohibited

× = don’t care

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