NEC PD754144 - Manual (Page 152)

CHAPTER 6 PERIPHERAL HARDWARE FUNCTION
152 User’s Manual U10676EJ3V0UM
Figure 6-40. Setting of Timer Counter Mode Registers
TM20 TM21 TM23 TM22 TM24 TM25 TM26 – TM2 F90H
TM23
Clears counter and IRQTn flag when "1" is written. Starts count operation
if bit 2 is set to "1".
Timer start command bit
Operation mode
TM22
0
1
Stops (count value retained)
Count operation
Count operation
Count pulse (CP) select bit
TMn6 TM1 TMn5
0 Overflow of count register (T2) 1
f X 2 5 1 0
0 1
1 f X /2 10 0
f X /2 8
f
X
/2 12
TMn4
0
1
0
1
1 1 0
f
X
/2 6 1 1 1
Operation mode select bit
TM21
1 16-bit timer counter mode
Mode TM20
0
7 6 5 4 3 2 1 0
TM10 TM11 TM13 TM12 TM14 TM15 TM16 –
Address
TM1 FA8H
Symbol
TM2
f
X
/2
f X
f X /2 8
f X /2 6
f
X
/2 10
f
X
/2 4
TM11
1
TM10
0
Setting prohibited Other
Remark n = 1 and 2