NEC PD754144 User Manual
Page 107
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION
107
User’s Manual U10676EJ3V0UM
Figure 6-15. Format of Processor Clock Control Register
PCC3
3
2
1
0
FB3H
Address
PCC
Symbol
PCC2 PCC1 PCC0
CPU operating mode control bits
PCC3
PCC2
Operating mode
0
0
Normal operating mode
0
1
HALT mode
1
0
STOP mode
1
1
Setting prohibited
CPU clock selection bits
(
µPD754144: When f
CC
= 1.0 MHz)
PCC1
PCC0
CPU clock frequency
1 machine cycle
0
0
Φ = f
CC
/64 (15.6 kHz)
64
µs
0
1
Φ = f
CC
/16 (62.5 kHz)
16
µs
1
0
Φ = f
CC
/8 (125 kHz)
8
µs
1
1
Φ = f
CC
/4 (250 kHz)
4
µs
(
µPD754244: When f
X
= 6.0 MHz)
PCC1
PCC0
CPU clock frequency
1 machine cycle
0
0
Φ = f
X
/64 (93.8 kHz)
10.7
µs
0
1
Φ = f
X
/16 (375 kHz)
2.67
µs
1
0
Φ = f
X
/8 (750 kHz)
1.33
µs
1
1
Φ = f
X
/4 (1.5 MHz)
0.67
µs
(
µPD754244: When f
X
= 4.19 MHz)
PCC1
PCC0
CPU clock frequency
1 machine cycle
0
0
Φ = f
X
/64 (65.5 kHz)
15.3
µs
0
1
Φ = f
X
/16 (262 kHz)
3.81
µs
1
0
Φ = f
X
/8 (524 kHz)
1.91
µs
1
1
Φ = f
X
/4 (1.05 MHz)
0.95
µs
Remark f
CC
and f
X
: System clock oscillation frequency