NEC PD754144 - Manual (Page 40)

CHAPTER 3 FEATURES OF ARCHITECTURE AND MEMORY MAP
40 User’s Manual U10676EJ3V0UM
(5) 8-bit register indirect addressing (@HL)
This addressing mode is used to indirectly address the entire data memory space in 8-bit units by using a data
pointer (HL register pair).
In this addressing mode, data is processed in 8-bit units, that is, the 4-bit data at an address specified by the
data pointer with bit 0 (bit 0 of the L register) cleared to 0 and the 4-bit data at the address higher are used
in pairs and processed with the data of the 8-bit accumulator (XA register).
The memory bank is specified in the same manner as when the HL register is specified in the 4-bit register
indirect addressing mode, by using MBE and MBS. This addressing mode is applicable to the MOV, XCH,
and SKE instructions.
Examples 1. To compare whether the count register (T0) value of timer counter 0 is equal to the data at addresses
30H and 31H
DATA EQU 30H
CLR1 MBE
MOV HL, #DATA
MOV XA, T0 ; XA
← count register 0
SKE XA, @HL ; XA = (HL)?
2. To clear data memory at 004H to 07FH
CLR1 RBE
CLR1 MBE
MOV XA, #00H
MOV HL, #04H
LOOP : MOV @HL, XA ; (HL) ← XA
INCS L
INCS L
BR LOOP
INCS H
NOP
SKE H, #08H
BR LOOP