NEC PD754144 - Manual (Page 153)

CHAPTER 6 PERIPHERAL HARDWARE FUNCTION
153 User’s Manual U10676EJ3V0UM
(b) Timer counter control register (TC2)
In the 16-bit timer counter mode, set TC2 as shown in Figure 6-41 (for the format of TC2, refer to Figure
6-30 Format of Timer Counter Control Register).
TC2 is manipulated by an 8-, 4-, or bit manipulation instruction.
TC2 is cleared to 00H when the internal reset signal is asserted.
The flags shown by a solid line in Figure 6-40 are used in the 16-bit timer counter mode.
Do not use the flags shown by a dotted line in the 16-bit timer counter mode (clear these flags to 0).
Figure 6-41. Setting of Timer Counter Control Register
7 6 5 4 3 2 1 0
NRZ NRZB TOE2 REMC – – – 0 TC2
Symbol
Timer counter output enable flag
TOE2
0
1
Disabled (low level output)
Enabled
Timer Output