NEC PD754144 - Manual (Page 76)

CHAPTER 4 INTERNAL CPU FUNCTION
76 User’s Manual U10676EJ3V0UM
(3) Interrupt status flags (IST1 and IST0)
The interrupt status flags record the status of the processing under execution (for details, refer to Table 7-3 IST,
IST0, and Interrupt Servicing).
Table 4-5. Contents of Interrupt Status Flags
IST1 IST0 Status of Processing Being Executed Processing and Interrupt Control
0 0 Status 0 Normal program is being executed.
All interrupts can be acknowledged
0 1 Status 1 Interrupt with lower or higher priority is serviced.
Only an interrupt with higher priority can be acknowledged
1 0 Status 2 Interrupt with higher priority is serviced.
All interrupts are disabled from being acknowledged
1 1 — Setting prohibited
The interrupt priority controller (refer to Figure 7-1 Block Diagram of Interrupt Control Circuit) identifies the
contents of these flags and controls the nesting of interrupts.
The contents of IST1 and 0 are saved to the stack along with the other bits of PSW when an interrupt is
acknowledged, and the status is automatically updated by one. When the RETI instruction is executed, the values
before the interrupt was acknowledged are restored to the interrupt status flags.
These flags can be manipulated by using a memory manipulation instruction, and the processing status under
execution can be changed by program.
Caution To manipulate these flags, be sure to execute the DI instruction to disable the interrupts before
manipulation. After manipulation, execute the EI instruction to enable the interrupts.
(4) Memory bank enable flag (MBE)
This flag specifies the address information generation mode of the higher 4 bits of the 12 bits of a data memory
address.
MBE can be set or reset at any time by using a bit manipulation instruction, regardless of the setting of the
memory bank.
When this flag is set to “1”, the data memory address space is expanded, and the entire data memory space
can be addressed.
When MBE is reset to “0”, the data memory address space is fixed, regardless of MBS (refer to Figure 3-2
Configuration of Data Memory and Addressing Ranges of Respective Addressing Modes).
When the RESET signal is asserted, the contents of bit 7 of program memory address 0 are set. Also, MBE
is automatically initialized.
When a vector interrupt is serviced, bit 7 of the corresponding vector address table is set. Also, the status
of MBE when the interrupt is serviced is automatically set.
Usually, MBE is reset to 0 for interrupt servicing, and the static RAM in memory bank 0 is used.