NEC PD754144 - Manual (Page 119)

CHAPTER 6 PERIPHERAL HARDWARE FUNCTION
119 User’s Manual U10676EJ3V0UM
Initial setting
6.3.5 Operation as watchdog timer
The basic interval timer/watchdog timer operates as a watchdog timer that asserts the internal reset signal when
an overflow occurs in the basic interval timer (BT), if WDTM is set to “1”. However, if the overflow occurs during the
oscillation wait time that elapses after the STOP instruction has been released, the reset signal is not asserted. (Once
WDTM has been set to “1”, it cannot be cleared by any means other than reset.) BT is always incremented by the
clock supplied from the clock generator, and its count operation cannot be stopped.
In the watchdog timer mode, a program hang-up is detected by using the interval time at which BT overflows. As
this interval time, four values can be selected by using bits 2 to 0 of BTM ( µPD754244 only. Refer to Figure 6-21).
Select the interval time best-suited to detecting a hang-up that may occur in your system. Set an interval time, divide
the program into several modules that can be executed within the set interval time, and execute an instruction that
clears BT at the end of each module. If this instruction that clears BT is not executed within the set interval time (in
other words, if a module of the program is not normally executed, i.e., if a hang-up occurs), BT overflows, the internal
reset signal is asserted, and the program is terminated forcibly. Consequently, assertion of the internal reset signal
indicates occurrence and detection of a program hang-up.
Set the watchdog timer as follows (<1> and <2> may be performed simultaneously).
<1> Set interval time to BTM.
<2> Set bit 3 of BTM to “1”.
<3> Set WDTM to “1”.
<4> After setting <1> to <3> above, set bit 3 of BTM to “1” within the interval time.