NEC PD754144 - Manual (Page 54)

CHAPTER 3 FEATURES OF ARCHITECTURE AND MEMORY MAP
54 User’s Manual U10676EJ3V0UM
Figure 3-7. µPD754244 I/O Map (3/8)
Hardware name (symbol)
Number of bits that
Bit
Address R/W
can be manipulated
manipulation Remarks
b3 b2 b1 b0 1-bit 4-bit 8-bit
addressing
FA0H Timer counter 0 mode register (TM0) R/W (W) – mem.bit Bit manipulation can be performed only on bit 3
– – –
FA2H TOE0 Note 1 – – – W – – mem.bit
FA3H Unmounted
FA4H Timer counter 0 count register (T0) R – – –
FA6H Timer counter 0 modulo register (TMOD0) R/W – – –
FA8H Timer counter 1 mode register (TM1) R/W (W) – mem.bit Bit manipulation can be performed only on bit 3
– – –
FAAH TOE1 Note 2 – – – W – – mem.bit
FABH Unmounted
FACH Timer counter 1 count register (T1) R – – –
FAEH Timer counter 1 modulo register (TMOD1) R/W – – –
Notes 1. TOE0: Timer counter output enable flag (channel 0) (W)
2. TOE1: Timer counter output enable flag (channel 1) (W)