NEC PD754144 - Manual (Page 93)

CHAPTER 6 PERIPHERAL HARDWARE FUNCTION
93 User’s Manual U10676EJ3V0UM
Figure 6-8. P7n Configuration (n = 0 to 3)
One-shot pulse generator
Key return reset
V
DD
Pull-up resistor
(mask option)
P70/KR4
P71/KR5
P72/KR6
P73/KR7
Interrupt control
Falling edge detector
Internal bus
Input buffer
Input buffer with
hysteresis characteristics
Figure 6-9. P80 Configuration
PM8
P80
Port mode register group C bit 0
Input buffer
Output latch
POGA bit 0 V DD
Pull-up resistor
P-ch
Internal bus
MPX
Output buffer
Input buffer with
hysteresis characteristics