NEC PD754144 - Manual (Page 138)

CHAPTER 6 PERIPHERAL HARDWARE FUNCTION
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User’s Manual U10676EJ3V0UM
(b) Timer counter control register (TC2)
In the 8-bit timer counter mode, set TC2 as shown in Figure 6-32 (for the format of TC2, refer to Figure
6-30 Format of Timer Counter Control Register).
TC2 is manipulated by an 8- or 4-bit, or bit manipulation instruction.
The value of TC2 is cleared to 00H when the internal reset signal is asserted.
The flags shown by a solid line in the figure below are used in the 8-bit timer counter mode.
Do not use the flags shown by a dotted line in the figure below in the 8-bit timer counter mode (clear these
flags to 0).
Figure 6-32. Setting of Timer Counter Control Register
7 6 5 4 3 2 1 0
NRZ NRZB TOE2 REMC – – – 0 TC2
Symbol
Timer counter output enable flag
TOE2
0
1
Disabled (low level output)
Enabled
Timer output
Figure 6-33. Setting of Timer Counter Output Enable Flag
TOE0
Address
FA2H Channel 0
TOE1 FAAH Channel 1
0 Disabled (low level output)
1 Enabled
Timer counter output enable flag (W)
(2) Time setting of timer counter