Artesyn MVME2500 ECC Installation and Use (August 2014) - Manual (Page 80)

Functional Description
MVME2500-ECC Installation and Use (6806800N30F) 80
4.13 I
2
C Devices
The MVME2500-ECC utilizes one of the two I2C ports provided by the board's processor. The
I
2 C bus is a two-wire , serial data (SDA) and serial clock (SCL), synchronous, multi-master bi-
directional serial bus that allows data exchance between this device and other devices such as
VPD, SPD, EEPROM, RTC, temperature sensor, RTM, XMC and IDT clocking.
The RTM I2C address can be configured by the user and should not contain duplicate addresses
to avoid conflict. For more information, see
I2C Bus Device Addressing, on page 124 .
4.14 Reset/Control FPGA
The FPGA provides the following functions:
 Power control and fault detection
 Reset sequence and reset management
 Status and control registers
 Miscellaneous control logic
 Watchdog timer
 32-bit Tick Timer
 Clock generator
 Switch decoder and LED controller
4.15 Power Management
The MVME2500-ECC backplane is utilized to derive +3.3V, +2.5V, +1.8V, +1.5V, +1.2V, +1.05V
voltage rail. Each voltage rail is controlled by the FPGA through an enable pin of the regulator,
while the output is monitored through power good signal. If a voltage rail fails. the FPGA will
disable each supply. To restart the system, the chassis power switch must be powercycled.