Artesyn MVME2500 ECC Installation and Use (August 2014) - Manual (Page 71)

Functional Description
MVME2500-ECC Installation and Use (6806800N30F) 71
4.2.13 Common On-Chip Processor (COP)
The COP is the debug interface of the QorIQ P20x0 Processor. It allows a remote computer
system to access and control the internal operation of the processor. The COP interface
connects primarily through the JTAG and has additional status monitoring signals. The COP has
additional features like breakpoints, watch points, register and memory
examination/modification and other standard debugging features.
4.2.14 P20x0 Hardware Configuration Pins
A series of strapping pins are required to initialize the P20x0. These pins are samples during the
assertion of HRESET and return to their assigned function after HRESET is deasserted.
4.3 System Memory
The processor integrated memory controller supports one channel of DDR3 memory with
either 1GB DDR3 (1Gbx8 devices) or 2GB DDR3 (2Gbx8 devices). The MVME2500 supports two
banks of memory. It comes with either 1 GB or 2 GB ECC SDRAM.
The MVME2500 is produced in a memory-down configuration, rather than a SODIMM
configuration. This enables product ruggedization for more demanding operating
environments. Eighteen memory devices provide 2 GB of ECC memory using 1 Gbit (256M x8)
device densities or 2GB of ECC memory using 2 Gbit (256M x8) device densities.
The MVME2500-ECC has a total of six board variants; four of which are commercial
temperature and have both 2GB and 1GB of memory, whereas the other two variants are
Extended Temperature (ET) and have 2GB of memory.
4.4 Timers
The MVME2500-ECC platform implements the following timer functions.
4.4.1 Real Time Clock
This operates on a 3.3 V supply monitoring and battery control function (MAX6364PUT29), a
32.768 KHz clock generator (DS32KHZS) and an RTC with alarm (DS1375T).