Artesyn MVME2500 ECC Installation and Use (August 2014) - Manual (Page 102)

Memory Maps and Registers
MVME2500-ECC Installation and Use (6806800N30F) 102
5.4.16 PLD Watchdog Timer Refresh Register
The MVME2500-ECC provides a watchdog timer refresh register.
Clear_Cause Clear Reset Reason (self clearing)
1 - Clear Reason
0 - None
CPU_RESET CPU_HRESET_REQ_L Reset Reason
1 - Reset is due to CPU_HRESET_REQ_L signal
0 -None
WD_TIMEOUT Watchdog Timeout Reset Reason
1 - Reset is due to watchdog timing out
0 - None
LRSTO TSI LRSTO Reset Reason
1 - Reset is due to LRSTO signal
0 - None
Sft_RST Soft Reset - Reset Reason
1 - Reset is due to Soft_RST register being set, or the front
panel switch being pressed more than three
0 - None
Table 5-18 PLD Watchdog Timer Refresh Register
REG PLD Watch Dog Timer Load - 0xFFC80600
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Field RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD Refresh
OPER R
RESET 0000
Field Description
Refresh Counter Refresh. When the pattern 0x00DB is written, the watchdog counter
will be reset to zero.