Altera Floating-Point - Manual (Page 79)

Figure 9-3: ALTFP_EXP Signals
data[]
clk_en
clock
inst
ALTFP_EXP
result[]
underflow
zero
nan
underflow
aclr
Table 9-4: ALTFP_EXP IP Core Input Signals
Port Name Required Description
aclr
No Asynchronous clear. When the
aclr
port is asserted high the function
is asynchronously reset.
clk_en
No Clock enable. When the
clk_en
port is asserted high, an exponential
value operation takes place. When this signal is asserted low, no
operation occurs and the outputs remain unchanged.
clock
Yes Clock input to the IP core.
data[]
Yes Floating-point input data. The MSB is the sign, the next MSBs are the
exponent, and the LSBs are the mantissa. This input port size is the
total width of the sign bit, exponent bits, and mantissa bits.
Table 9-5: ALTFP_EXP IP Core Output Signals
Port Name Required Description
result[]
Yes The floating-point exponential result of the value at
data[]
. The MSB
is the sign, the next MSBs are the exponent, and the LSBs are the
mantissa. The size of this port is the total width of the sign bit,
exponent bits, and mantissa bits.
overflow
No Overflow exception output. Asserted when the result of the operation
(after rounding) is infinite.
underflow
No Underflow exception output. Asserted when the result of the exponen‐
tial approaches
1
(from numbers of very small magnitude), or when
the result approaches
0
(from negative numbers of very large
magnitudes).
zero
No Zero exception output. Asserted when the value in the
result[]
port
is zero.
UG-01058
2014.12.19
ALTFP_EXP Signals 9-5
ALTFP_EXP IP Core Altera Corporation
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