Altera Floating-Point User Manual
Page 146
Family
Input
Precisi
on
Output
Width
Output
Fractio
n
Latenc
y
f
MAX
ALMs
M10K
M20K
DSP
Blocks
Logic Registers
Primar
y
Secondary
Stratix V
(5SGXEA7
K2F40C2)
Single
32
0
0
717.36
168
--
0
0
38
0
32
16
0
717.36
168
--
0
0
38
0
32
32
0
717.36
168
--
0
0
38
0
64
0
0
717.36
304
--
0
0
70
0
64
16
0
717.36
304
--
0
0
70
0
64
32
0
717.36
304
--
0
0
70
0
Doubl
e
32
0
0
717.36
204
--
0
0
38
0
32
16
0
717.36
204
--
0
0
38
0
32
32
0
717.36
204
--
0
0
38
0
64
0
2
456
329
--
0
0
134
1
64
16
2
456
329
--
0
0
134
1
64
32
2
456
329
--
0
0
134
1
Arria 10
(10AX115H
4F34I3SP)
Single
32
0
0
--
168
--
0
0
38
0
32
16
0
--
168
--
0
0
38
0
32
32
0
--
168
--
0
0
38
0
64
0
0
--
304
--
0
0
70
0
64
16
0
--
304
--
0
0
70
0
64
32
0
--
304
--
0
0
70
0
Doubl
e
32
0
0
--
203
--
0
0
38
0
32
16
0
--
203
--
0
0
38
0
32
32
0
--
203
--
0
0
38
0
64
0
2
407.33
328
--
0
0
134
0
64
16
2
407.33
328
--
0
0
134
0
64
32
2
407.33
328
--
0
0
134
0
UG-01058
2014.12.19
ALTERA_FP_FUNCTIONS Resource Utilization and Performance
18-19
ALTERA_FP_FUNCTIONS IP Core
Altera Corporation
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)