Altera Floating-Point - Manual (Page 147)

Table 18-5: FXPFP
Family
Input
Width
Input
Fractio
n
Output
Precisi
on
Latenc
y
f
MAX
ALMs M10K M20K
DSP
Blocks
Logic Registers
Primar
y
Secondary
Arria V
(5AGX
FB3H4
F40C5)
32 0 Single 6 283.61 154 0 -- 0 195 14
32 0 Doubl
e
5 328.19 165 0 -- 0 180 17
32 16 Single 6 283.61 154 0 -- 0 195 14
32 16 Doubl
e
5 328.19 165 0 -- 0 180 17
32 32 Single 6 293 152 0 -- 0 193 13
32 32 Doubl
e
5 336.59 159 0 -- 0 180 16
64 0 Single 7 282.01 217 0 -- 0 297 16
64 0 Doubl
e
7 256.48 330 0 -- 0 451 18
64 16 Single 7 282.01 217 0 -- 0 297 16
64 16 Doubl
e
7 256.48 330 0 -- 0 451 18
64 32 Single 7 282.01 217 0 -- 0 297 16
64 32 Doubl
e
7 256.48 330 0 -- 0 451 18
18-20 ALTERA_FP_FUNCTIONS Resource Utilization and Performance
UG-01058
2014.12.19
Altera Corporation ALTERA_FP_FUNCTIONS IP Core
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