Altera Floating-Point User Manual
Page 106
Table 15-1: ALTFP_ABS Resource Utilization and Performance for the Stratix III Device Family
Precision
Output
Latency
Logic usage
f
MAX
(MHz)
Adaptive
Look-Up
Tables
(ALUTs)
Dedicated
Logic
Registers
(DLRs)
18-Bit DSP
Memory
Single
0
0
0
0
0
The f
MAX
of this IP
core depends on the
speed of the selected
device
1
0
36
0
0
Double
0
0
0
0
0
1
0
68
0
0
ALTFP_ABS Design Example: Absolute Value of Multiplication Results
This design example uses the ALTFP_ABS IP core to compute the absolute value of the multiplication
result of single-precision format numbers. This example incorporates the ALTFP_MULT IP core and uses
the parameter editor in the Quartus II software.
Related Information
•
Floating-Point IP Cores Design Example Files
on page 1-16
•
Provides the design example files for the Floating-Point IP cores
•
Provides information about installation, usage, and troubleshooting
ALTFP_ABS Design Example: Understanding the Simulation Results
The simulation waveform in this design example is not shown in its entirety. Run the design example files
in the ModelSim-Altera software to see the complete simulation waveforms.
Figure 15-1: ALTFP_ABS Simulation Waveform
This design example produces a floating-point absolute value function for the multiplication results of
single-precision format numbers. All the optional input ports (
clk_en
and
aclr
) and optional output
ports (
overflow
,
underflow
,
zero
,
division_by_zero
, and
nan
) are enabled.
15-2
ALTFP_ABS Design Example: Absolute Value of Multiplication Results
UG-01058
2014.12.19
Altera Corporation
ALTFP_ABS IP Core