Altera Floating-Point - Manual (Page 20)

Figure 1-9: Single-Precision Representation
This figure shows a single-precision representation.
S E M
31 30 23 22 0
Double-Precision Format
The double-precision format contains the following binary patterns:
• The MSB holds the sign bit.
• The next 11 bits hold the exponent bits.
• 52 LSBs hold the mantissa.
The total width of a floating-point number in the double-precision format is 64 bits. The bias for the
double-precision format is 1023.
Figure 1-10: Double-Precision Representation
This figure shows a double-precision representation.
S E M
63 62 52 51 0
Single-Extended Precision Format
The single-extended precision format contains the following binary patterns:
• The MSB holds the sign bit.
• The exponent and mantissa fields do not have fixed widths.
• The minimum exponent field width is 11 bits and must be less than the width of the mantissa field.
• The width of the mantissa field must be a minimum of 31 bits.
The sum of the widths of the sign bit, exponent field, and mantissa field must be a minimum of 43 bits
and a maximum of 64 bits. The bias for the single-extended precision format is unspecified in the
IEEE-754 standard. In these IP cores, a bias of
2
( WIDTH_EXP–1 ) –
1
is assumed for the single-extended
precision format.
Special Case Numbers
The following table lists the special case numbers defined by the IEEE-754 standard and the data bit
representations.
Table 1-4: Special Case Numbers in IEEE-754 Representation
Meaning Sign Field Exponent Field Mantissa Field
Zero Don’t care All 0’s All 0’s
Positive Denormalized 0 All 0’s Non-zero
1-14 Double-Precision Format
UG-01058
2014.12.19
Altera Corporation About Floating-Point IP Cores
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