Altera Floating-Point - Manual (Page 100)

Table 13-2: ALTFP_ATAN Resource Utilization and Performance
Device Family Function Precision
Output
Latency
Logic usage
f
MAX
(MHz)
Adaptive
Look-Up
Tables
(ALUTs)
Dedicate
d Logic
Registers
(DLRs)
Adaptive
Logic
Modules
(ALMs)
18-Bit
DSP
Stratix V ArcTange
nt
Single 36 2,454 1,010 1,303 27 255.49
Ports
Table 13-3: ALTFP_ATAN Megafunction Input Ports
Port Name Required Description
aclr
No Asynchronous clear. When the
aclr
port is asserted high, the
function is asynchronously cleared.
clk_en
No Clock enable. When the
clk_en
port is asserted high, division
takes place. When the signal is deasserted, no operation occurs
and the outputs remain unchanged.
clock
Yes Clock input to the megafunction.
data[]
Yes Floating-point input data. The MSB is the sign bit, the next MSBs
are the exponent, and the LSBs are the mantissa. This input port
size is the total width of the sign bit, exponent bits, and mantissa
bits.
Port Name Required Description
result[]
Yes The result of the trigonometric function in floating-point format.
The widths of the
result[]
output port and
data[]
input port
are the same.
ALTFP_ATAN Parameters
13-2 Ports
UG-01058
2014.12.19
Altera Corporation ALTFP_ATAN IP Core
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