Altera Floating-Point User Manual
Page 135

Family
Function
Precision Latency
f
MAX
ALMs
M10K M20
K
DSP
Blocks
Logic Registers
Primary Secondary
Arria 10
(10AX115H4
F34I3SP)
Abs
Single
0
--
33
--
0
0
0
0
Double
0
--
65
--
0
0
0
0
Add
Single
4
296.4
49
--
0
1
0
0
Double
7
296.3
840
--
0
0
779
67
AddSubtra
ct
Single
5
319.39
483
--
0
0
408
37
Double
7
289.77
1,106
--
0
0
1,006
156
Cube Root
Single
10
432.9
126
--
5
2
121
0
Double
24
282.09
594
--
11
10
1,155
29
Divide
Single
16
347.34
394
--
3
4
561
66
Double
30
258.26
1,208
--
20
15
2,175
136
Exp base
10
Single
14
271.37
502
--
3
2
432
40
Double
29
242.42
2,185
--
0
10
1,683
90
Arria 10
(10AX115H4
F34I3SP)
Exp base 2
Single
7
317.86
370
--
0
2
124
9
Double
22
251.45
906
--
0
10
1,172
47
Exp base e
Single
26
365.36
298
--
3
6
137
11
Double
28
260.42
2,156
--
0
10
1,724
93
Reciprocal
Single
12
278.94
225
--
3
3
172
3
Double
27
260.89
824
--
9
14
1,448
100
Reciprocal
Square
Root
Single
8
418.94
117
--
3
2
130
1
Double
22
243.43
523
--
8
9
950
37
LDExp
Single
0
--
68
--
0
0
0
0
Double
0
--
99
--
0
0
66
0
Log base
10
Single
15
293.69
364
--
3
3
441
42
Double
28
272.03
1,158
--
20
11
2,095
214
Log(1+x)
Single
18
301.3
747
--
3
3
882
79
Double
32
251.95
2,018
--
20
13
3,019
248
18-8
ALTERA_FP_FUNCTIONS Resource Utilization and Performance
UG-01058
2014.12.19
Altera Corporation
ALTERA_FP_FUNCTIONS IP Core
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)