Altera Floating-Point - Manual (Page 2)

Contents
About Floating-Point IP Cores........................................................................... 1-1
List of Floating-Point IP Cores.................................................................................................................. 1-1
Installing and Licensing IP Cores..............................................................................................................1-2
Design Flow.................................................................................................................................................. 1-2
IP Catalog and Parameter Editor...................................................................................................1-3
Specifying IP Core Parameters and Options................................................................................1-4
Specifying IP Core Parameters and Options (Legacy Parameter Editors)...............................1-8
Upgrading IP Cores.....................................................................................................................................1-9
Migrating IP Cores to a Different Device...................................................................................1-12
Floating-Point IP Cores General Features..............................................................................................1-12
IEEE-754 Standard for Floating-Point Arithmetic............................................................................... 1-13
Floating-Point Formats.................................................................................................................1-13
Special Case Numbers................................................................................................................... 1-14
Rounding.........................................................................................................................................1-15
Non-IEEE-754 Standard Format.............................................................................................................1-15
Floating-Points IP Cores Output Latency..............................................................................................1-16
Floating-Point IP Cores Design Example Files......................................................................................1-16
VHDL Component Declaration.............................................................................................................. 1-18
VHDL LIBRARY-USE Declaration.........................................................................................................1-18
ALTERA_FP_MATRIX_INV IP Core................................................................2-1
ALTERA_FP_MATRIX_INV Features.................................................................................................... 2-1
ALTERA_FP_MATRIX_INV Output Latency....................................................................................... 2-1
ALTERA_FP_MATRIX_INV Resource Utilization and Performance................................................2-1
ALTERA_FP_MATRIX_INV Functional Description.......................................................................... 2-2
Cholesky Decomposition Function...............................................................................................2-3
Triangular Matrix Inversion...........................................................................................................2-5
Matrix Multiplication......................................................................................................................2-5
Matrix Inversion Operation........................................................................................................... 2-5
ALTERA_FP_MATRIX_INV Design Example: Matrix Inverse of Single-Precision Format
Numbers.................................................................................................................................................. 2-6
ALTERA_FP_MATRIX_INV Design Example: Understanding the Simulation Results..... 2-7
Sample Matrix Data.....................................................................................................................................2-8
ALTERA_FP_MATRIX_INV Signals.....................................................................................................2-10
ALTERA_FP_MATRIX_INV Parameters............................................................................................. 2-11
ALTERA_FP_MATRIX_MULT IP Core............................................................3-1
ALTERA_FP_MATRIX_MULT Features................................................................................................3-1
ALTERA_FP_MATRIX_MULT Output Latency...................................................................................3-1
ALTERA_FP_MATRIX_MULT Resource Utilization and Performance........................................... 3-1
ALTERA_FP_MATRIX_MULT Functional Description......................................................................3-2
TOC-2
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