Altera Floating-Point User Manual
Page 43
Table 4-1: ALTERA_FP_ACC_CUSTOM Resource Utilization and Performance
This table lists the resource utilization and performance information for the ALTERA_FP_ACC_CUSTOM IP
core. The information was derived using the Quartus II software version 13.1.
Device
Family
Input Data
Accumulator
Size
Targe
t
Frequ
ency
(MHz)
Laten
cy
ALMs
DSP
Block
s
Logic
Registers
M10K M20K
f
MAX
Floati
ng
Point
Form
at
MaxM
SBX
MSBA LSBA
Prima
ry
Secon
dary
Arria
V
(5AG
XFB3
H4F4
0C5)
Doub
le
24
40
-52
270
15
866
0
1,166
106
0
--
265
Cyclo
ne V
(5CG
XFC7
D6F3
1C7)
Doub
le
24
40
-52
230
15
830
0
1,102
32
0
--
198
Stratix
V
(5SG
XEA7
K2F40
C2)
Doub
le
24
40
-52
400
15
968
0
1,655
27
--
0
426
Arria
V
(5AG
XFB3
H4F4
0C5)
Single
12
20
-26
270
12
337
0
588
52
0
--
309
Cyclo
ne V
(5CG
XFC7
D6F3
1C7)
Single
12
20
-26
230
12
383
0
494
28
0
--
225
Stratix
V
(5SG
XEA7
K2F40
C2)
Single
12
20
-26
400
13
475
0
903
20
--
0
450
4-2
ALTERA_FP_ACC_CUSTOM Resource Utilization and Performance
UG-01058
2014.12.19
Altera Corporation
ALTERA_FP_ACC_CUSTOM IP Core
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)