Altera Floating-Point - Manual (Page 36)

ALTERA_FP_MATRIX_MULT IP Core
3
2014.12.19
UG-01058 Subscribe
Send Feedback
ALTERA_FP_MATRIX_MULT Features
The ALTERA_FP_MATRIX_MULT IP core offers the following features:
• Multiplication of two matrices.
• Support for floating-point formats in single and double precisions.
• Support for configurable performance and resource usage.
• Avalon streaming interfaces and full QSys compliance.
ALTERA_FP_MATRIX_MULT Output Latency
The ALTERA_FP_MATRIX_MULT IP core does not have a fixed output latency. Instead, the IP core
uses Avalon streaming interfaces and the
c_valid
signal on the output interface to indicate when output
data is available.
ALTERA_FP_MATRIX_MULT Resource Utilization and Performance
These tables list the resource utilization and performance information for the
ALTERA_FP_MATRIX_MULT IP core. The information was derived using the Quartus II software
version 14.1.
© 2014 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are
trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html . Altera warrants performance
of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,
product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.
ISO
9001:2008
Registered
www.altera.com
101 Innovation Drive, San Jose, CA 95134