Altera Floating-Point - Manual (Page 25)

ALTERA_FP_MATRIX_INV IP Core
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2014.12.19
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ALTERA_FP_MATRIX_INV Features
The ALTERA_FP_MATRIX_INV IP core offers the following features:
• Inversion of a matrix.
• Support for floating-point format in single precision.
• Support for VHDL and Verilog HDL languages.
• Support for matrix sizes up to are 4 × 4, 6 × 6, 8 × 8, 16 ×16, 32 × 32, and 64 × 64.
• Use of control signal,
load
.
• Use of handshaking signals:
busy
,
outvalid
, and
done
.
ALTERA_FP_MATRIX_INV Output Latency
The ALTERA_FP_MATRIX_INV IP core does not have a fixed output latency. Instead, it uses
handshaking signals to interface with external circuitry.
ALTERA_FP_MATRIX_INV Resource Utilization and Performance
This table lists the resource utilization and performance information for the ALTERA_FP_MATRIX_INV
IP core. The information was derived using the Quartus II software version 10.0
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