Altera Floating-Point User Manual
Page 141

Family
Function Precision Scale
By Pi
Latenc
y
f
MAX
ALM
s
M10K M20K
DSP
Blocks
Logic Registers
Primary
Secondary
Stratix V
(5SGXEA
7K2F40C
2)
Arccos
Single
0
23
291.4
6
753
--
9
8
801
34
Single
1
27
288.4
3
823
--
9
9
891
27
Double
0
53
247.4
6
2,38
0
--
27
37
4,435
145
Double
1
58
233.1
5
2,57
0
--
27
40
4,717
121
Arcsin
Single
0
20
290.6
1
598
--
9
8
698
19
Single
1
23
294.9
9
678
--
9
9
800
21
Double
0
47
237.2
5
2,23
5
--
27
40
4,407
89
Double
1
52
240.3
3
2,41
1
--
27
43
4,621
134
Arctan
Single
0
20
293.6 544
--
6
6
646
53
Single
1
23
290.7 620
--
6
7
715
50
Double
0
47
241.7
2
1,83
7
--
18
30
3,424
145
Double
1
52
247.3
4
2,00
2
--
18
33
3,654
126
Arctan2
Single
0
31
288.3
5
890
--
9
9
1,277
71
Single
1
31
288.3
5
890
--
9
9
1,277
71
Double
0
69
239.2
3
2,98
3
--
29
42
5,530
212
Double
1
69
239.2
3
2,98
3
--
29
42
5,530
212
18-14
ALTERA_FP_FUNCTIONS Resource Utilization and Performance
UG-01058
2014.12.19
Altera Corporation
ALTERA_FP_FUNCTIONS IP Core
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)