Altera Floating-Point User Manual
Page 138

Family
Function Precision Scale
By Pi
Latenc
y
f
MAX
ALM
s
M10K M20K
DSP
Blocks
Logic Registers
Primary
Secondary
Arria V
(5AGXFB
3H4F40C
5)
Arctan2
Single
0
43
230.2 1,01
3
11
--
9
1,719
128
Single
1
43
230.2 1,01
3
11
--
9
1,719
128
Double
0
92
184.2 3,19
5
44
--
43
6,822
285
Double
1
92
184.2 3,19
5
44
--
43
6,822
285
Cos
Single
0
25
205.3 768
5
--
6
1,563
120
Single
1
12
242.1
3
490
0
--
3
475
36
Double
0
45
184.2 2,87
9
34
--
33
5,973
244
Double
1
29
185.8
7
1,71
9
0
--
13
2,499
92
Arria V
(5AGXFB
3H4F40C
5)
Sin
Single
0
26
223.5
1
964
5
--
6
1,439
110
Single
1
12
240.5
6
585
0
--
3
563
66
Double
0
46
184.1
6
3,01
9
36
--
33
6,308
249
Double
1
29
185.7
7
1,74
8
0
--
14
2,699
92
Tan
Single
0
38
221.7
8
1,36
8
12
--
12
2,625
163
Single
1
25
231.4
3
1,29
7
4
--
10
1,512
140
Double
0
68
185.5
6
5,21
1
56
--
65
10,670
530
Double
1
52
184.1
6
3,87
4
26
--
43
6,896
238
UG-01058
2014.12.19
ALTERA_FP_FUNCTIONS Resource Utilization and Performance
18-11
ALTERA_FP_FUNCTIONS IP Core
Altera Corporation
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)