Altera Floating-Point User Manual
Page 133

Family
Function
Precision Latency
f
MAX
ALMs
M10K M20
K
DSP
Blocks
Logic Registers
Primary Secondary
Cyclone V
(5CGXFC7D
6F31C7)
Log base e
Single
22
181.42
482
4
--
3
1,058
45
Double
50
196.27
1,941
40
--
13
4,611
197
Multiply
Single
6
268.6
159
0
--
1
223
2
Double
11
205.17
431
0
--
4
970
18
Power
Single
62
181.19
1,778
11
--
14
3,562
154
Double
127
186.53
5,411
22
--
38
12,361
325
Square
Root
Single
8
219.15
126
3
--
2
205
12
Double
31
250
822
8
--
9
2,056
55
Subtract
Single
12
232.07
399
0
--
0
566
42
Double
20
204.25
918
0
--
0
1,839
60
Stratix V
(5SGXEA7K
2F40C2)
Abs
Single
0
--
33
--
0
0
0
0
Double
0
--
65
--
0
0
0
0
Add
Single
5
364.83
366
--
0
0
299
19
Double
7
329.49
834
--
0
0
801
53
AddSubtra
ct
Single
5
354.74
489
--
0
0
411
29
Double
7
338.41
1,106
--
0
0
1,039
134
Cube Root
Single
8
420.17
114
--
5
2
124
11
Double
20
277.7
520
--
11
10
997
17
Divide
Single
13
363.5
377
--
3
4
591
71
Double
23
270.86
1,091
--
20
15
2,274
120
Exp base
10
Single
11
292.4
486
--
3
2
417
12
Double
22
271.74
2,033
--
0
10
1,761
48
18-6
ALTERA_FP_FUNCTIONS Resource Utilization and Performance
UG-01058
2014.12.19
Altera Corporation
ALTERA_FP_FUNCTIONS IP Core
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)