Altera Floating-Point User Manual
Page 140

Family
Function Precision Scale
By Pi
Latenc
y
f
MAX
ALM
s
M10K M20K
DSP
Blocks
Logic Registers
Primary
Secondary
Cyclone V
(5CGXFC
7D6F31C
7)
Arctan2
Single
0
51
206.1
4
1,15
3
11
--
9
2,013
149
Single
1
51
206.1
4
1,15
3
11
--
9
2,013
149
Double
0
144
191.1
7
4,58
9
46
--
43
10,740
417
Double
1
144
191.1
7
4,58
9
46
--
43
10,740
417
Cos
Single
0
32
174.6
7
959
5
--
6
2,258
110
Single
1
15
212.9
9
517
0
--
3
702
25
Double
0
75
182.7
5
3,75
1
34
--
33
9,177
352
Double
1
50
212.6
8
1,98
5
0
--
13
3,914
169
Sin
Single
0
33
191.6
1
1,08
6
5
--
6
2,394
132
Single
1
14
207.8
1
579
0
--
3
783
39
Double
0
75
196.3
9
3,78
7
38
--
33
9,545
284
Double
1
49
206.5
3
2,16
5
0
--
14
4,336
177
Tan
Single
0
46
185.7
4
1,65
5
12
--
12
3,738
200
Single
1
29
205.4
7
1,28
3
4
--
10
2,142
102
Double
0
112
194.7 7,05
2
58
--
65
16,793
607
Double
1
89
197.2
4
5,32
7
26
--
43
11,741
376
UG-01058
2014.12.19
ALTERA_FP_FUNCTIONS Resource Utilization and Performance
18-13
ALTERA_FP_FUNCTIONS IP Core
Altera Corporation
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)