Altera Floating-Point User Manual
Page 143

Family
Function Precision Scale
By Pi
Latenc
y
f
MAX
ALM
s
M10K M20K
DSP
Blocks
Logic Registers
Primary
Secondary
Arria 10
(10AX115
H4F34I3S
P)
Arccos
Single
0
28
270.4
2
703
--
9
8
656
29
Single
1
31
261.2
3
705
--
9
9
624
19
Double
0
63
257.8 2,62
6
--
27
37
4,917
241
Double
1
69
255.6
2
2,81
3
--
27
40
5,127
268
Arcsin
Single
0
25
249.6
3
665
--
9
8
659
18
Single
1
28
254.1
9
673
--
9
9
649
30
Double
0
57
255.6
2
2,44
0
--
29
40
4,750
213
Double
1
62
251.5
1
2,59
6
--
29
43
4,985
190
Arctan
Single
0
26
271.3 600
--
6
6
578
32
Single
1
29
274.2 594
--
6
7
583
22
Double
0
57
254.1
3
1,86
6
--
22
30
3,654
171
Double
1
63
258.3
3
2,04
3
--
22
33
3,726
253
Arctan2
Single
0
40
248.1
4
1,00
2
--
9
9
1,258
85
Single
1
40
248.1
4
1,00
2
--
9
9
1,258
85
Double
0
84
255.1 3,02
5
--
33
42
5,675
328
Double
1
84
255.1 3,02
5
--
33
42
5,675
328
18-16
ALTERA_FP_FUNCTIONS Resource Utilization and Performance
UG-01058
2014.12.19
Altera Corporation
ALTERA_FP_FUNCTIONS IP Core
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)