Maxim Integrated Secure Microcontroller - Manual (Page 96)

Secure Microcontroller User’s Guide
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Interrupt Enable Control Bits
All bits are read/write at any time and are cleared to 0 following any hardware reset.
IE.7
EA
Enable All Interrupts When set to 1, each interrupt except for PFW may be individually enabled or
disabled by setting or clearing the associated IE.x bit. When cleared to 0,
interrupts are globally disabled and no pending interrupt request will be
acknowledged except for PFW.
IE.4
ES
Enable Serial Interrupt When set to 1, an interrupt request from either the serial port’s TI or RI flags
can be acknowledged. Serial I/O interrupts are disabled when cleared to 0.
IE.3
ET1
Enable Timer 1 Interrupt When set to 1, an interrupt request from Timer 1’s TF1 flag can be
acknowledged. Interrupts are disabled from this source when cleared to 0.
IE.2
EX1
Enable External Interrupt 1 When set to 1, an interrupt from the IE1 flag can be acknowledged. Interrupts
are disabled from this source when cleared to 0.
IE.1
ET0
Enable Timer 0 Interrupt When set to 1, an interrupt request from Timer 0’s TF0 flag can be
acknowledged. Interrupts are disabled from this source when cleared to 0.
IE.0
EX0
Enable External Interrupt 0 When set to 1, an interrupt request from the IE0 flag can be acknowledged.
Interrupts are disabled from this source when cleared to 0.
11.7 Interrupt Priorities
The secure microcontroller provides a three priority interrupt scheme. Multiple priority levels allow
higher priority sources to interrupt lower priority ISRs. The Power-fail Warning Interrupt automatically
has the highest priority if enabled. The user can program the remaining interrupts to either high or low
priority. The priority scheme works as follows. The ISR for a low priority source can be interrupted by a
high priority source. A low priority ISR cannot be interrupted by another low priory source. Neither can a
high priority ISR be interrupted by a another high priority source. The PFW source will interrupt any ISR
if activated.
In the case of simultaneous interrupt requests, the microcontroller has a natural scheme to arbitrate. First,
if high and low priority interrupt requests are received simultaneously, then the high priority source will
be serviced. If two or more requests from equal priority sources are received, the following natural
priority scheme will be used to arbitrate.