Maxim Integrated Secure Microcontroller - Manual (Page 111)

Secure Microcontroller User’s Guide
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TCON Register Control/Status Bits
TCON.7 TF1
Timer 1 Overflow Flag Status bit set to 1 when Timer 1 overflows from a previous count value of all 1’s.
Cleared to 0 when CPU vectors to Timer 1 Interrupt service routine.
Initialization: Cleared to 0 on any type of reset.
TCON.6
TR1
Timer 1 Run Control When set to a 1 by software, Timer 1 operation will be enabled. Timer 1 is
disabled when cleared to 0.
Initialization: Cleared to 0 on any type of reset.
TCON.5
TF0
Timer 0 Overflow Status bit set to 1 when Timer 0 overflows from a previous count value of all 1’s.
Cleared to 0 when CPU vectors to Timer 0 interrupt service routine.
Initialization: Cleared to 0 on any type of reset.
TCON.4
TR0
Timer 0 Run Control When set to 1 by a software, Timer 0 operation is enabled. Timer 0 is disabled
when cleared to 0.
Initialization: Cleared to 0 on any type of reset.
13.2 Mode 0
Figure 13-1 is a block diagram of a timer/counter operating in Mode 0. Mode 0 configures either
programmable timer for operation as a 13-bit timer/counter. For Timer 0, selection of Mode 0 configures
bit 4–0 of TL0 as bits 4–0 respectively of the 13-bit timer/counter register. In addition, bits 7–0 of TH0
are configured as bits 12–5 respectively of the 13-bit timer/counter register. Bits 7–5 of TL0 are
indeterminate and should be ignored when read. All of the timer/counter bits are cleared to 0 by a
hardware reset. When the TR0 bit is set with either GATE = 0 or
INT0 = 1, the 13-bit register will be
incremented as each count is received. The previous value of the 13-bit register is the TR0 bit is set to a 1
from a previous 0 condition.
When the 13-bit timer/counter reaches a value of 1FFFH (all 1s) the next count received will cause the
value to roll over to 0000 and the TF0 flag will be set. Additionally, an interrupt will be generated if it
had been enabled.
Mode 0 operation for Timer 1 is functionally identical to that described for Timer 0. TH1 and TL1 are
used to form the 13-bit register as just described for Timer 0. Likewise, TR1, TF1, and INT1 perform the
functions described for TR0, TF0, and
INT0 .
13.3 Mode 1
Mode 1 for both programmable timers operates in an identical fashion described for Mode 0, except
Mode 1 configures a 16-bit timer/counter register. In this case, for Timer 0, TH0 contains the most
significant eight bits of the count value while TL0 holds the least significant eight bits. Timer 1 uses TH1,
TL1 in an identical fashion in Mode 1.
Figure 13-1 is also a diagram depicting operation in Mode 1 for
the timer/counters.