Maxim Integrated Secure Microcontroller - Manual (Page 21)

Secure Microcontroller User’s Guide
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The second bus is an expanded bus constituted by Ports 0 and 2. This is the standard 8051-compatible
memory bus that is available as an option, but is not needed in most cases. Program memory on the
expanded bus must be ROM/EPROM and data memory must be volatile SRAM. If NV RAM is needed
on the expanded bus, then it must be externally backed up and write protected. The secure microcontroller
makes no special provisions for NV RAM on the expanded bus. When discussing memory addressing of
secure microcontrollers, there are two important terms that are used frequently–partition and range. The
partition is the user-selectable address that divides the program segment from the data segment in a
common RAM area on the bytewide bus. The partition is a user-adjustable boundary that can be selected
during bootstrap loading or on the fly by the application software. The range is the total amount of
memory connected to the bytewide bus. This is set once during initial programming.
The DS5000 series devices can access up to 8kB and 64kB of NV RAM on the bytewide bus. Up to the
first 32kB are partitionable into program and data segments as described above. The DS5001/DS5002
series can access between 8kB and 128kBs on its bytewide bus with better partition control. The memory
map control resides in the MCON (address C6h) SFR on DS5000 devices. The DS5001 devices use the
MCON (address C6h) and RPCTL (address D8h) registers. Since the memory maps and control have
significant differences between these versions, they are described later in separate sections.
4.2 DS5000 Series Memory Organization
As mentioned above, the DS5000 series consists of the DS5000FP chip and the DS5000(T) and DS2250T
modules. The programming model discussed in this section applies to all of these parts. The DS5000FP
bytewide bus has 15 address lines, eight data lines, a R/
W strobe, and two chip enables to access NV
RAM. In the case of a module, these are already connected and can be thought of as internal or embedded
memory. The DS5000 series can use either 8kB x 8 or 32kB x 8 SRAMs, selected using the range bit
(MCON.3) and has a value of 0 when 8kB SRAM is used and 1 when a 32kB SRAM is used. Range is
selected during bootstrap loading and cannot be varied by the application software. The DS5000FP
accesses memory on its bytewide bus using two chip enables. The first,
CE1 , is partitionable. That is, the
RAM connected to CE1 , whether 8kB or 32kB, can be divided between program and data segments. The
partition is user-selected and can be set during bootstrap loading and by software. Partitions are available
on 2kB boundaries in the DS5000, except for the last, which is 4kB. The partition is selected using the
MCON SFR described below.
CE2 is restricted to data memory only. The RAM on CE2 should be of the
same size as CE1 . Access to CE2 is controlled by ECE2 bit (MCON.2) and is described below.
Figure 4-3 illustrates the functional memory map of a DS5000 series device. The partition, range, ECE2,
and the logical address combine to determine whether the DS5000 uses its bytewide bus or the expanded
bus. NV RAM access occurs when the logical address lies in one of the shaded regions. These are
program addresses below the partition address, data addresses above the partition and below the range
address, or data addresses between 0 and the range when ECE2 is set to a logic 1. Note that when using
ECE2 to force data access, the
CE2 RAM is selected instead of the CE1 RAM. This means that on a
DS5000 module or a DS2250 with less than 64kB RAM, no data memory exists under CE2 . The ECE2
has no affect on program memory, which continues from the CE1 RAM or the expanded bus normally.
Note that the partition and range settings are not automatically linked, allowing a user to accidentally
select a partition that is larger than the range. When the range is 32kB, the partition address can be as high
as 32kB. When a range of 8kB is used, partition addresses below 8kB should be used. Any address that
does not map onto the bytewide bus is automatically routed to the expanded bus of Ports 0 and 2. For
module users, this means that any address not routed to internal memory goes to the ports.