Maxim Integrated Secure Microcontroller - Manual (Page 88)

Secure Microcontroller User’s Guide
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The distinguishing action taken during a power-on reset is that the
POR bit is cleared in order to indicate
that a power-on reset has just occurred. All other control bits that are initialized according to the type of
reset are left unchanged from their previous condition.
10.1.2 No-V
LI
Power-On Reset
During a power-on reset cycle, at the end of the power-on reset-delay time, internal circuitry measures the
voltage on the V
LI
pin of the microprocessor. If V
LI
<~0.8V, a no-V
LI
power-on reset is initiated and SFR
are initialized during the rest as shown in Table 10-A . These include:
1) The POR bit (PCON.6) is cleared to indicate that a power-on reset has just occurred.
2) The watchdog timer is disabled by writing a 0 into the EWT bit (PCON.2).
3) The partition address bits (PA3-0) are set to all 1s. In addition, the range function is set to select a
32kB address space for the RAM.
4) On a DS5000, the encryption key and software encryption operation are disabled.
5) Finally, the security lock bit is cleared to 0.
10.1.3 External Reset
For applications that require an external reset capability, a reset pin (RST) is provided with a Schmitt
trigger input. This input can be used to force a reset condition any time when the micro is executing the
application program or when it is in either the idle or stop modes. Reset is initiated by holding the RST
pin active (high) for a minimum time of two machine cycles (24 clock oscillator periods). If the reset was
initiated from stop mode, the rising edge results in an internally generated power-on reset time (t
POR
),
which is required for the oscillator to start and for the clock frequency to stabilize.
All the control bits that are initialized according to the type of reset within the SFRs are left unchanged
from their previous condition following an external reset. Note: An RC circuit should not be used on the
reset pin to generate a power-on reset.
10.1.4 Watchdog Timer Reset
The on-chip watchdog timer is provided as a method of restoring proper software operation in the event
that software control is lost. The watchdog timer is enabled via the EWT bit (PCON.2). This bit can only
be written by using the timed-access function.
Once the watchdog timer is initialized, an internal reset is issued if the software fails to reset the timer via
the RWT bit (IP.7) at least once before it reaches its timeout condition. The timeout period is equal to
122,880 machine cycles. If a 12MHz crystal is used as the time-base element, this gives a timeout period
of 122.88ms. To reset the watchdog timer in the application software, the RWT bit must be written with a
1 using the timed-access procedure. The watchdog timer is also reset following any other type of reset.
When a watchdog timer reset occurs, special initialization is performed on the SFRs, as shown in
Table 10-A . The distinguishing action taken during this type of reset is that the WTR status flag is set to
indicate that a watchdog timer reset has just occurred.
Application: Reset Routine Example
Like the 8051, Maxim microcontrollers will begin execution at address 0000h. This is the Reset Vector,
followed by other vector locations used for interrupts. These are discussed in the section covering
interrupt operation. Since there are only three memory locations dedicated to the Reset Vector, the user
will typically insert a jump statement to a more convenient memory address. This will be the reset