Maxim Integrated Secure Microcontroller - Manual (Page 58)

Secure Microcontroller User’s Guide
58 of 187
6. LITHIUM/BATTERY BACKUP
Soft microcontroller devices are battery backed for data retention in the absence of V
CC
. The state of the
microcontroller in the soft microcontroller is also maintained, unlike a conventional processor system
using an external NV RAM. This section discusses the battery-backup feature, covering system design,
battery attach procedure, I/O pin restrictions, lifetime calculations, and battery/RAM size tradeoffs. Some
information is unnecessary to module users but it provides background information for proper handling
and system design. Each section highlights both chip and module considerations when there are
differences.
When properly used, secure microcontrollers provide better than 10 years of data retention in the absence
of power at room temperature. Elevated temperatures can cause increased normal data retention current to
be drawn by a RAM. Data retention current is only a concern when the device is in battery-backed mode
as no current is drawn from the battery while +5V is applied to the device. Therefore, data retention must
be viewed in the context of the power supply duty cycle. For example, if a system is rated for 10 years of
data retention, but will have power applied for 12 hours per day, the expected lifetime is greater than 20
years, or the lifetime of the battery, whichever is less.
6.1 Data Retention
The secure microcontroller family provides nonvolatile storage in ordinary SRAM. It accomplishes this
by battery backing the memory in the absence of power. When power (V
CC
) begins to fail, the processor
generates an internal power-fail reset condition as discussed in the next section. At this time, SRAM chip
enables are taken to a logic high inactive state. Also, I/O port pins also go to a logic high state. If power
continues to fall and crosses below the battery threshold, the microprocessor enters the data retention
state, and the microcontroller’s power-supply output to the SRAM (V
CCO
) is switched from V
CC
to the
battery. Battery-backed chip enables are maintained at a logic high state, but nonbacked chip enables and
I/O port pins follow V
CC
down. Maintaining chip enables at an inactive level and lowering the power
supply to approximately +3V causes the NV RAM to enter a data retention state. Thus the combination
retains data for a long period as the circuits draw a very small current from the battery. Maxim soft/secure
microcontroller modules easily exceed 10 years of data retention, and solutions can be designed using
discrete Maxim soft/secure microcontroller chips, SRAMs and batteries to achieve a much greater
lifetime as required by the user’s application.
Battery-Backed Circuits
The secure microcontroller is completely battery-backed, meaning that both internal configuration and
data are preserved when power is removed. In order to achieve this ultra-low power state, special logic in
the microprocessor places all internal nodes in a predictable (low power) state. This occurs during system
power-down while V
CC
is falling below the reset voltage threshold but is still above the battery voltage
(V
LI
). To allow time for the internal battery control circuitry to switch from V
CC
to battery power
,
the
power supply must allow at least 40 µs (130 µs for DS5001/DS5002) between the V
CCMIN
and V
LI
.
Failure to meet this condition may result in an incomplete transition to battery-backed mode, resulting in
a substantial increase in microprocessor backup current (in excess of the data sheet specification) and/or
program/data corruption. Fortunately, a modest amount of system capacitance is enough to prevent fast
slewing. The actual value will depend on the total system loading. This slew rate must be met for either a
chip or module solution.
Figure 6-1 illustrates the power supply conditions that should be met.