Maxim Integrated Secure Microcontroller - Manual (Page 71)

Secure Microcontroller User’s Guide
71 of 187
MOV
0C7H, #0AAh ; 1st TA Value
MOV 0C7H, #055h ; 2nd TA Value
SETB IP.7 ; Reset Watchdog Timer
If the timeout period expires without the timer being reset by the software, the Watchdog Timer will reset
the CPU, set the WTR status flag (regardless of whether the reset is enabled), and start counting again.
The WTR flag allows the application software to distinguish this type of reset from other reset so that
special processing can be performed to accommodate this case. The WTR bit is cleared only by a read of
the PCON register. Therefore, this register should be read during initialization following a reset in order
to properly interpret the source of the reset. The Watchdog Timer is also reset by any other type of reset
and will begin its count as soon as the reset condition is released.
The Watchdog Timer Reset Bit (WTR) is held in a logic 1 state for 8192 clock cycles following the time-
out of the watchdog 122,880 cycle counter. During this time, the bit may be read but attempts to clear the
bit will fail. This condition will not be noticed if the Enable Watchdog Timer bit (EWT) is set, because
the 8192 cycle count will be reset during the device reset triggered by the watchdog time-out. The bit may
then be cleared, if desired, during application’s power-on reset routine.
Some applications may use the watchdog timer but not set the EWT bit, preferring instead to poll the
WTR bit in software to detect a watchdog time-out. In this case, one approach is for the application
software to continually read the EWT bit as long as it is set. When the 8192 clock cycle period is
complete, the last read of the EWT bit will successfully clear the bit and exit the routine. Alternatively,
software can poll the WTR bit until it is set, then reset the watchdog via the RWT bit to clear the 8192
cycle count. The next read of the PCON register will clear WTR bit as expected.
8.3 CRC Memory Verification
When using nonvolatile memory, there is always the potential for a catastrophic event to alter the
memory contents. These events include lightning, massive ESD, severe mistreatment, etc. No nonvolatile
technology is immune to these events. To compensate, the DS5001/DS5002 series contain circuitry that
enables the microcontroller to perform a CRC function, as summarized below. The DS5002FP does not
support the automatic CRC on power-up feature because the sequential memory access of a CRC could
make it easier for a outsider to gain information about the system.
PART AUTOMATIC CRC ON POWER-UP HARDWARE SUPPORT FOR SOFTWARE CRC
DS5000FP Not Supported Not Supported
DS5001FP Yes Yes
DS5002FP Not Supported Yes
8.3.1 Automatic CRC on Power-Up Feature
If the CRC option is selected through the Bootstrap Loader, then on power up or after a Watchdog Timer
reset, the microcontroller will automatically perform a CRC-16 on the memory. The range over which it
is performed is selected by the user, and the result is compared to a pre-stored value. If the CRC-16 is in
error, the DS5001 series microcontroller will enter the Bootstrap Loader and wait. From the perspective
of the system, the appears held in a reset condition.