Maxim Integrated Secure Microcontroller - Manual (Page 132)

Secure Microcontroller User’s Guide
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In the 2-byte 1-cycle instruction shown in Figure 15-3(B) , the op code is read during S1 while the second
byte of the instruction, or the operand, is read during S4. Again, execution of the instruction is complete
at the end of S6P2.
A 1-byte, 2-cycle instruction is shown in
Figure 15-3(C) . In this case the op-code byte is read at S1 of the
first machine cycle. The next op code is then read three times during the S1 and S4 of the second machine
cycle. The information is discarded each of these times until it is finally read when the next instruction is
actually executed.
Finally,
Figure 15-3(D) illustrates the execution of one of the MOVX instruction that is also a 1-byte, 2-
cycle instruction. However, the execution timing of this unique in that a data memory location is accessed
during the execution of the instruction. This access takes place during the time period from S4 of the first
cycle through S3 of the second cycle. If the access is made from data memory mapped on the expanded
bus, then ports P0, P2, and pins P3.6 and P3.7 will automatically be enabled and the read or write
operation will take place on external memory. If the access is made from data memory space which is
mapped within the bytewide RAM, then the read or write operation will take place on the bytewide RAM
bus and the external port pins will not be affected.
15.3 Expanded Program Memory Timing
A program memory access will occur on the expanded bus any time that instructions are executed from
program memory space that is mapped outside of the bytewide RAM. Mapping of program memory on
the expanded bus is dependent on the programming of the partition, range, the state of the external
EA
pin, and the internal security lock. See Section 4 for a detailed discussion on program memory mapping.
The external timing for the expanded program memory fetch cycle is illustrated in
Figure 15-4 . A full 16-
bit address is always output on the multiplexed expanded bus (P2, P0) pins whenever such an access is
performed. The high-order 8 bits are output on the P2 pins while the low-order eight bits are output on the
P0 pins. Strong pullups are enabled onto Ports 0 and 2 for the duration of time that 1s are output on the
port for address bits. As long as program memory is being executed from the expanded bus, P0 and P2
pins are unavailable for use as general-purpose I/O.
Multiplexed address and data information appear on the Port 0 pins as program memory fetches are
performed on the expanded bus. The falling edge of ALE can be used to signal when the lowest eight bits
of valid address information are being output on Port 0 when such a fetch occurs. In addition, ALE is
activated twice every machine cycle during access to program memory, regardless of whether the fetch
takes place to RAM or to the expanded bus. Whenever a program memory fetch takes place on the
expanded bus, the SFR latch for Port 0 is written with all 1s (0FFH) so that the original information
contained in this register is lost. Port 0 pins are driven with internal buffers when 1s are output during
expanded program memory cycles.
The
PSEN signal is provided as the read strobe pulse for expanded program memory fetches. When the
secure microcontroller is accessing program memory from bytewide RAM,
PSEN remains inactive.
During program memory fetches on the expanded bus, it is activated twice every machine cycle, except
when a MOVX instruction is being executed. As discussed in the previous section, not all bytes fetched
from expanded program memory are actually used by the CPU during instruction execution. A complete
memory cycle, including the enabled and disabling of both ALE and
PSEN, takes six clock oscillator
periods. This is one-half of a machine cycle.