Maxim Integrated Secure Microcontroller - Manual (Page 5)

Secure Microcontroller User’s Guide
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LIST OF FIGURES
Figure 3-1. Secure Microcontroller Architectural Block Diagram .............................................................. 15
Figure 4-1. Secure Microcontroller Memory Map ..................................................................................... 18
Figure 4-2. Scratchpad Register Map ....................................................................................................... 20
Figure 4-3. DS5000 Series Memory Map ................................................................................................. 23
Figure 4-4. Partitionable Memory Map for DS5001/DS5002 Series ......................................................... 26
Figure 4-5. Nonpartitionable Memory Map for DS5001/DS5002 Series ................................................... 27
Figure 4-6. Peripheral Enables in the Data Memory Map......................................................................... 28
Figure 4-7. Reloading Portions of a DS5000 Series Device ..................................................................... 31
Figure 4-8. Reloading a DS5001/DS5002 Series Device ......................................................................... 33
Figure 4-9. DS5000 SFR Map .................................................................................................................. 34
Figure 4-10. DS5001/DS5002 SFR Map .................................................................................................. 35
Figure 5-1. Memory Interconnect of the DS5000FP ................................................................................. 51
Figure 5-2. DS5000 Series Module Block Diagram .................................................................................. 52
Figure 5-3. Memory Interconnect of the Partitionable DS5001/DS5002 ................................................... 53
Figure 5-4. Memory Interconnect of the Nonpartitionable DS5001FP, DS5002FP .................................. 54
Figure 5-5. Memory Interconnect Using the 128kB SRAM ....................................................................... 55
Figure 5-6. DS2251T-128 Block Diagram ................................................................................................ 56
Figure 5-7. DS2252T-32 Block Diagram .................................................................................................. 57
Figure 6-1. Power-Supply Slew Rate ....................................................................................................... 59
Figure 7-1. Secure Microcontroller Power Cycling Timing........................................................................ 65
Figure 7-2. Secure Microcontroller Power Management .......................................................................... 67
Figure 8-1. Timed Access ......................................................................................................................... 69
Figure 8-2. CRC Code Example ............................................................................................................... 73
Figure 9-1. DS5000 Software Encryption Block Diagram ......................................................................... 76
Figure 9-2. DS5002 Software Encryption Block Diagram ......................................................................... 77
Figure 9-3. Dummy Bus Access Timing ................................................................................................... 80
Figure 10-1. Power-On Reset Timing ....................................................................................................... 87
Figure 11-1. Interrupt Request Sources ................................................................................................... 95
Figure 11-2. Interrupt Acknowledge Sequence ........................................................................................ 98
Figure 12-1. Port 0 Functional Circuitry .................................................................................................. 100
Figure 12-2. Port 1 Functional Circuitry .................................................................................................. 100
Figure 12-3. Port 2 Functional Circuitry .................................................................................................. 101
Figure 12-4. Port 3 Functional Circuitry .................................................................................................. 101
Figure 12-5. Parallel Port Output Buffers (Ports 1, 2, and 3) .................................................................. 103
Figure 12-6. Use of the RPC Mode ........................................................................................................ 105
Figure 13-1. Timer/Counter Mode 0 and 1 Operation ............................................................................ 112
Figure 13-2. Timer/Counter Mode 2 Operation ...................................................................................... 113
Figure 13-3. Timer 0 Mode 3 Operation ................................................................................................. 113
Figure 14-1. Mode 0 Block Diagram And Timing .................................................................................... 122
Figure 14-2. Serial Port Mode 1 Block Diagram ..................................................................................... 123