Maxim Integrated Secure Microcontroller - Manual (Page 120)

Secure Microcontroller User’s Guide
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The SHCLK signal will be initially output low on the TXD pin starting at S3P1 of the same machine
cycle in which D0 was sampled. As in the case described above for transmit, SHCLK will be low during
S3, S4, and S5 and high during S6, S1, and S2 of every machine cycle.
After the last data bit (D7) has been shifted in, the control logic will immediately load the Receive Data
Buffer at the SBUF register address with the contents of the Receive Shift register. At S1P1 of the 10
th
machine cycle following the write to SCON that initiated reception, the Receive Interrupt flag will be set
and a serial interrupt will be generated if it has been enabled.
14.4 Asynchronous Operation
Mode 1, 2, and 3 provide asynchronous, full-duplex communication via the Serial I/O Port. The serial
data word is either 10 or 11 bits long, depending on the mode selected. All three modes include one start
bit, eight data bits, and one stop bit. Modes 2 and 3 include an additional, programmable 9th data bit.
TXD is used for serial data output, while RXD is used for serial data in-put. In all three modes, the serial
data word is both transmitted and received LSB first. The baud rate generator clock pulse (BRG clock) is
derived either from the Timer 1 overflow output or divided directly from the clock oscillator frequency
(of period t
CLK
). The following description applies to all three of the operational modes. Figure 14-2 is a
functional block diagram of the operation of the serial I/O port in Mode 1 including the timing
waveforms, which should be referred to in the discussion below.
Asynchronous serial data output begins whenever software writes to the SBUF register. When the write
operation occurs at the time indicated by the WRSBUF signal in the timing diagram, the contents of the
8-bit data bus will be loaded into bits D8–D1 of the Transmit Shift register. Simultaneously, a 0 is loaded
into the D0 bit position of the shift register, and a 1 is loaded into the Stop bit position. (D9 for Mode 1,
D10 for Modes 2 or 3), factor of 16 by the hardware to establish the serial output bit rate. Following the
write operation to the Transmit Shift register, the LSB will be shifted out to the output latch of the TXD
pin at the next time the divide-by-16 counter rolls over to zero. This counter is not synchronized to the
machine cycles associated with instruction execution. As a result, data transmission will commence
anywhere from 0 to 16 of the Baud Rate Generator clocks from the time that the Transmit Shift register is
written. Successive bits from the Transmit Shift register will be shifted into the output latch of the TXD
pin each time the divide-by-16 counter rolls over to zero. As each shift right operation is performed, a 0 is
shifted into the MSB position from the left. When the Stop bit is shifted into the latch, the shifting
operation is complete and the TI flag will be set. A serial interrupt will be generated if it has been
enabled.
The Baud Rate Generator clock output is fed directly into the Bit Detector to perform serial data
reception. Reception begins when a valid start bit of 0 is detected on the RXD pin. The Bit Detector will
determine when this has occurred as follows: On each BRG clock pulse, the RXD pin will be sampled for
a 1-to-0 transition. When such a transition is recognized, the Bit Detector will then reset its own internal
divide-by-16 counter and sample the RXD pin on the 7th, 8th, and 9th BRG clock times following the
transition. If a logic 0 level is detected on two out of these three sample times, a valid start bit is assumed.
Otherwise, the Bit Detector will reject the incoming signal as a start bit and will repeat the process by
searching for another 1-to-0 transition on RXD. If a valid start bit is detected, the RXD pin will be
sampled in the middle of each successive bit time until the entire 10-bit or 11-bit serial word has been
received. Following the detection of a valid start bit, successive bit times begin each time that the Bit
Detector’s divide-by-16 counter rolls over to 0. During each bit time, the RXD pin is sampled on the 7
th
,
8th, and 9th BRG clock times. For the data bits, the logic level, which is read at least two out of the three