Maxim Integrated Secure Microcontroller - Manual (Page 62)

Secure Microcontroller User’s Guide
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7. POWER MANAGEMENT
All secure microcontrollers are implemented using CMOS circuitry for low power consumption. Two
software-initiated modes are available for further power saving at times when processing is not required
and V
CC
is at normal operating voltage. These are the idle and stop modes. The additional third mode is
the data retention or zero-power state, which is made possible by the on-chip circuitry. The control and
status bits that apply to these operating modes are contained in the PCON register and are summarized in
Control/Status Bits for Power Control. In addition,
Table 7-A summarizes the state of external pins in
each of these modes.
7.1 Idle Mode
Idle mode suspends activity of the CPU but allows the timer/counters, I/O pins, and serial port to continue
their operation. This greatly reduces the number of switching nodes and thereby dramatically reduces the
total power consumption of the device. Idle mode is useful for applications in which lower power
consumption is desired with fast response to external interrupts but no other processing.
Software invokes idle mode by setting the IDL bit (PCON.0) to a logic 1. The instruction that sets this bit
is the last instruction executed before idle mode operation begins. Once in idle mode, the microprocessor
preserves the entire CPU status including the stack pointer, program counter, program status word,
accumulator, and RAM. There are two ways to terminate the idle mode. The first is from an interrupt that
has been previously enabled prior to entering idle mode. This will clear the IDL bit and cause the CPU to
enter the interrupt service routine as normal. When the RETI instruction is executed, the next instruction
that is executed is the one that immediately follows the instruction that set the IDL bit.
The second method of terminating the idle mode is by a reset. At this time the IDL bit is cleared and the
CPU is placed in the reset state. Since the clock oscillator continues to run in the idle mode, an oscillator
startup delay (referred to as t
POR
in the AC Electrical Specifications in the data sheet) is not generated
following the reset. Two machine cycles are required to complete the reset operation (24 oscillator
periods). It should be noted that the watchdog timer continues to run during idle and that a reset from the
on-chip watchdog timer terminates idle mode.