Maxim Integrated Secure Microcontroller - Manual (Page 24)

Secure Microcontroller User’s Guide
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DS5000 SERIES MCON REGISTER
MCON.7–4 PA3–0
Partition Address Use to select the starting address of data memory in embedded RAM. Program
space lies below the partition address.
MCON.3
RA32/8
Range Address Sets the maximum usable address on the bytewide bus. RA32/8 = 0 sets range
address = 1FFFH (8kB); RA32/8 = 1 sets range address = 7FFFH (32kB)
MCON.2
ECE2
Enable Chip Enable 2 Used to enable or disable the CE2 signal to additional RAM data memory space.
When ECE2 = 0, all MOVX instructions activate the CE1 signal. When ECE2 = 1,
all MOVX instructions activate the CE2 signal. This bit should always be cleared
to 0 in the DS5000-8, DS5000-32, DS2250-8, and DS2250-32 modules.
MCON.1
PAA
Partition Address Access Used to protect the programming of the partition address select bits. PA3–0 cannot
be written when PAA = 0. PAA can be written only via the timed-access register.
4.4 DS5001/DS5002 Memory Organization
Note that the DS5002FP is a high-security version of the DS5001FP, but has the same memory map and
I/O. The programming model discussed in this section applies to all of these parts and any reference to
the DS5001 applies to all of them. The DS5001 series bytewide bus has 16 address lines, eight data lines,
a R/
W strobe, and a total of eight chip enables to access NV RAM and peripherals. Chip enables include
CE1 - CE4 and PE1 - PE4 . The four chip enables ( CE1 -4) are for NV RAM access. How they are connected
depends on the memory mode and the selection of SRAMs. The PE signals are generally for memory-
mapped peripherals, but can be used for more RAM if desired. PE1 and PE2 are lithium-backed, PE3 and
PE4 are not. In the case of a module, PE1 may be connected to a RTC. Memory map control resides in
the MCON (C6h) and RPCTL (D8h) registers. The MCON register has selected differences from its
DS5000 counterpart. These are documented below. The RPCTL is not present in the DS5000. Also, not
all of the bits in this register pertain to memory map control. This section describes the relevant bits and
the SFR section below documents the entire register.
The DS5001/DS5002 series can use multiple 8kB x 8 or 32kB x 8 SRAMs or a single 128kB x 8 SRAM.
These parts can operate in either a partitionable (like DS5000) or nonpartitionable mode. The mode is
selected via the PM (MCON.1) bit of the MCON register. Note that the DS5001 MCON provides
different functions than the DS5000. In partitionable mode (PM = 0), the DS5001/DS5002 can use up to
64kB x 8 SRAM for program and data on its bytewide bus. It can partition this area into program and data
segments on 4kB boundaries. The 64kB memory space would consist of two 32kB x 8 SRAMs. Each is
accessed by a separate chip enable (
CE1 and CE2 ), but the microcontroller automatically decodes which
is needed.
While the DS5001/DS5002 can use between one 8kB x 8 SRAM and four 32kB x 8 SRAMs, it does not
automatically know which configuration is used. The user must identify the total RAM size using the
range bits RG1 and RG0. RG1 is located at MCON.3 and RG0 is located at RPCTL.0. These range bits