Maxim Integrated Secure Microcontroller - Manual (Page 64)

Secure Microcontroller User’s Guide
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7.2 Stop Mode
Stop mode is initiated by setting the STOP bit (PCON.1). The operation of the oscillator is halted in stop
mode so that no internal clocking signals are produced for either the CPU or the I/O circuitry. An external
reset via the RST pin is the only means of exiting this mode without powering down (V
CC
taken below
V
CCMIN
) and then backing up to produce a power-on reset. The STOP bit can only be set by using the
timed-access software procedure described in Section 8 . Since the oscillator is disabled in this mode, the
watchdog timer also ceases operation. When the external reset signal is issued to terminate the Stop
mode, a 21,504-clock delay is generated to allow the clock oscillator to start up and its frequency to
stabilize as is done for a power-on reset as described in Section
10 . The original contents of those SFRs
that are initialized by a reset are lost.
7.3 Voltage Monitoring Circuitry
The on-chip voltage monitoring circuitry automatically places the microprocessor in its data retention
state when V
CC
< V
CCMIN
. It ensures that the proper internal control signals are generated and that power
from the battery is applied at the proper times so that the program/data RAM, data in the scratchpad
registers, and certain SFRs remain unchanged when V
CC
is cycled on and off. In addition, an interrupt is
available for signaling the processor of an impending power-fail condition so that the operational state of
the processor can be saved just prior to entering the data retention.
The voltage-monitoring circuitry recognizes three voltage thresholds below nominal operating voltage.
These thresholds are identified as V
PFW
(power-fail warning voltage), V
CCMIN
(minimum operating
voltage), and V
LI
(lithium supply) voltage. These thresholds are used to initiate required actions within
the microprocessor during situations when V
CC
power is cycled on and off. The timing diagram shown in
Figure 7-1 illustrates key internal activities during power cycling.
7.4 Power-Fail Interrupt
When V
CC
> V
CCMIN
, program execution proceeds as normal. If V
CC
should decay from its nominal
operating voltage and drop to a level below the V
PFW
threshold, the PFW status flag (PCON.5) is set. In
addition, a power-fail warning interrupt is generated if it has been enabled via the EPFW control bit
(PCON.3). The purpose of these indicators is to warn the processor of a potential power failure.
The V
PFW
threshold is above the specified minimum value for V
CC
(V
CCMIN
) for full processor operation.
The V
PFW
threshold is selected so that with a reasonable power-supply slew rate, ample time is allowed
for the application software to save all critical information which would otherwise be lost in the absence
of V
CC
. Such information can include the states of the accumulator, stack pointer, data pointer, and other
SFRs that are initialized with a reset when V
CC
voltage is applied once again. Saved data can be placed
into scratchpad RAM or bytewide NV RAM. Through the use of the power-fail warning interrupt, an
orderly shutdown of the system can be performed prior to the time that processor operation is halted in
the event that V
CC
voltage is removed entirely.
The PFW flag is set to a logic 1 whenever V
CC
< V
PFW
. It is cleared in one of two ways: a read of the
PFW bit from software, or a power-on reset. If V
CC
is still below the V
PFW
threshold when the bit is
cleared, the PFW bit is immediately set once again. An interrupt is generated any time both the EPFW bit
and the PFW flag are set.