Maxim Integrated Secure Microcontroller - Manual (Page 66)

Secure Microcontroller User’s Guide
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clock oscillator is allowed to start up and an internal power-on reset cycle is executed. Part of the cycle
involves a considerable delay that is generated to allow the clock oscillator frequency to stabilize.
Activity on the RST pin is ignored until this sequence is completed. The time required for this cycle is
shown as t
POR
in Figure 7-1 and is specified in the AC Electrical Specifications of the data sheet. A
detailed description of the power-on reset cycle operation is given in Section 10 .
Typically, the time taken for the power-on reset cycle is longer to complete than it takes for V
CC
to rise
above the V
PFW
threshold. In this case the internal PFW flag will be reset before execution of the user’s
program begins as illustrated in Figure 7-1 . If the power-on reset cycle completes before V
CC
>V
PFW
, PFW
is set again as a result of V
CC PFW
during user software execution. A power-fail interrupt occurs at this
time if the EPFW bit is enabled. A user should monitor the POR bit to know the power-supply status. See
to
Figure 7-2 for details.
7.6 Partial Power Failures
Two cases of partial power failure can occur in which V
CC
voltage does not go through a completed
power-fail cycle, as previously described. The first case is that in which V
CC
drops below the V
CCMIN
threshold and then returns to its nominal level without going below the V
LI
threshold. The second case is
that in which V
CC
drops below the V
PFW
threshold and then returns to its nominal level without going
below the V
CCMIN
threshold. Both of these cases are very possible in a system application and could be
caused by a “brownout” condition prom the power supply.
The first case is indistinguishable by the software from the complete power-fail cycle that was previously
described. When V
CC
drops below V
PFW,
the PFW flag is set and the clock oscillator stops when V
CC
drops below V
CCMIN
. The only operational difference is that if V
CC
never drops below the V
LI
threshold,
the internal power-supply line is never switched over to the lithium cell. When V
CC
rises back above the
V
CCMIN
threshold, the power-on reset cycle is executed as before. As a result, no special processing is
required in software to accommodate this case.
In the case that V
CC
dips without going below V
LI
, the PFW flag is set and a power-fail warning interrupt
still occurs when V
CC
drops below the V
PFW
threshold. The PFW flag remains set until it is cleared by
either a reset of the flag by the software or by a power-on cycle. If it is cleared while V
CC
is still below
the V
PFW
threshold, it is immediately set again. If it is cleared after V
CC
has risen back above the V
PFW
threshold, then it remains cleared until the next time V
CC
goes below V
PFW
.
As long as the PFW = 1, an interrupt occurs if EPFW is set. If the software executes a service routine in
response to a PFW interrupt and exits the service routine with the PFW flag still set, the processor is
immediately interrupted again. In a typical application, however, the power-fail interrupt service routine
would test the PFW flag in a conditional loop to determine if V
CC
has risen back above V
PFW
and would
then return control to the main program in response to the event. See Figure 7-2 for details.