Maxim Integrated Secure Microcontroller - Manual (Page 93)

Secure Microcontroller User’s Guide
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11.2 External Interrupts
The two external interrupts are
INT0 and INT1. They correspond to P3.2 and P3.3 respectively. These
pins become interrupts when the respective interrupt is enabled. Otherwise, they are simply port pins. No
other special action is required. Each pin is sampled once per machine cycle when the interrupts are
enabled. Setting the EX0 bit to logic 1 enables
INT0. Setting the EX1 bit to logic 1 enables INT1. These
bits are located at IE.0 and IE.2, respectively. The external interrupts each have a status flag that indicates
that the condition has occurred. The flags are IE0 at TCON.1 and IE1 at TCON.3. These flags are set to
logic 1 when the interrupt condition occurs. They are cleared when the CPU calls to the appropriate
interrupt vector.
The external interrupts can be programmed to respond to falling-edge or low-level activation. IT0
(TCON.0) and IT1 (TCON.2) control the edge/level nature of
INT0 and INT1, respectively. When ITn is
logic 0, the associated interrupt is low-level activated. This causes the IEn flag to be set for as long as the
INTn pin remains logic 0. The interrupt (if enabled) will remain active during this period. Note that the
level interrupt is not latched. Thus the pin must be held in a low state until the ISR can be activated. If the
INTn pin is brought to logic high prior to beginning the ISR, there will be no interrupt. If INTn is left at
logic low after the RETI instruction of the ISR, another interrupt will be activated after one instruction is
executed.
Setting the
INTn bit to logic 1 causes the external interrupt to be edge activated. This causes the device to
detect a falling edge on the
INTn pin. This edge condition is latched until the interrupt is serviced. Thus
in edge mode, the
INTn pin can go from logic 1 to logic 0, then back to logic 1 and the interrupt will still
be active. After the falling-edge has been detected, the
INTn pin is subsequently ignored until after the
ISR is complete. The edge detector is actually a “pseudoedge” detector. Since the pin is actually sampled,
the condition must be a logic high for at least one machine cycle and logic low for at least one machine
cycle in order to guarantee recognition of the falling edge. The IEn flag is automatically cleared when the
interrupt is serviced.
11.3 Timer Interrupts
The secure microcontroller, like the 8051, has two internal timers. These timers can each generate an
interrupt when the value in the timer registers overflows. When the Timer 0 overflows, the TF0 flag is set
to al logic 1. Likewise for the TF1 flag with respect to Timer 1. TF0 is located at TCON.5 and TF1 is
located at TCON.7. These flags indicate the overflow condition. If the corresponding timer interrupt is
desired, then ET0 at IE.1 and ET1 at IE.3 must be set to logic 1, respectively. When set, the timer
overflow will cause an interrupt to the appropriate vector location. If the interrupt is active, the CPU
automatically clears the flag.
11.4 Serial Port Interrupts
The on-chip serial port generates an interrupt when either a word is received or a word is transmitted. The
interrupt is effectively a logical OR of the two conditions. Each condition has its own flag. The flags
operate regardless of whether the interrupt has been enabled. RI is located at SCON.0 and represents a
serial word received. TI is located at SCON.1 and represents a serial word transmitted. Each flag is set to
logic 1 to indicate an active state. Since there are two flags for one interrupt, these flags are used by the
ISR to determine the cause of the interrupt. The flags must be cleared by software to clear the interrupt
condition. Setting the ES bit at IE.4 to logic 1 activates the serial interrupt.